The Leak That Actually Tells Us Something
Most pre-release Geekbench leaks are noise. Engineering silicon running at fractional clocks, BIOS microcode that isn't final, scheduler quirks that make Windows throw threads at the wrong cores — the performance numbers are almost always useless. This one isn't. A 10-core AMD engineering sample showed up on Geekbench 6.6.0 on March 16, 2026, under the platform string 'Plum-MDS1', and that codename alone tells you what you're looking at: Medusa Point, AMD's next-generation mobile APU built on Zen 6. Every nanometer counts, and this one is running on TSMC's N2 node.
The raw numbers: 10 cores, 20 threads, 10MB of L2 cache, 32MB of L3 cache, a 2.40GHz base clock, and actual run frequencies hovering around 2.01GHz. The chip scored 2,300 single-core and 13,002 multi-core. That's it. That's the leak.
And those numbers are shocking.
Why 2GHz Matters More Than 5GHz
Here's the math that should make Intel's architecture team nervous. A Ryzen AI 9 365 — also 10 cores, also Strix Point-class, but running Zen 5 — boosts to 5.0GHz on its performance cores and scores roughly 12,454 in Geekbench 6 multi-core. Medusa Point, at less than half that clock speed, posted 13,002. That's a 4.4% multi-thread lead at what amounts to 40% of the boost frequency.
Single-thread tells the same story in reverse. Medusa Point's 2,300 single-core at ~2GHz is only 7.3% behind Ryzen AI 9 365 running flat-out at 5GHz. Normalize for clock speed and you're looking at per-clock performance gains that are, frankly, hard to believe from a pre-production sample.
Let me translate that to architecture-speak: if these numbers survive to production silicon, Zen 6 is delivering IPC gains in a range AMD hasn't hit since Zen 3 crashed through Intel's lineup in 2020. The realistic uplift is probably 25-35% per clock over Zen 5 for this specific workload, which is the kind of generational jump we usually associate with major microarchitectural rewrites — not incremental tocks.
The 4+6 Core Config and What It Means
Medusa Point keeps the hybrid configuration AMD introduced with Strix Point: 4 classic Zen 6 cores plus 6 Zen 6c density-optimized cores. The 'c' cores aren't efficiency cores in the Intel sense — they run the same ISA, same full-width execution, same AVX-512 units. They just trade clock ceiling for area density by using a cell library tuned for smaller footprint rather than high frequency. Think of them as the same engine with a shorter redline.
The 32MB L3 cache is the interesting tell. Strix Point shipped with 24MB split across two CCXs. Going to 32MB unified (or in a revised topology) means either a larger physical cache slice per core, a change in how the two core clusters share L3, or — most likely — both. For mobile workloads that bounce threads between P and c cores, a larger shared last-level cache is exactly the kind of change that pays dividends in multi-thread scores like the one we're seeing.
The N2 Node Is Doing Real Work
TSMC's N2 node brings gate-all-around (GAAFET) transistors for the first time in a mass-market x86 chip. The transition from FinFET (N3 and earlier) to nanosheet GAAFET is a bigger physical change than the last three full node shrinks combined. Better electrostatics mean lower leakage, which means the 'c' cores can push higher sustained clocks without blowing thermal budget. It also means the kind of low-voltage efficiency that would let a 2GHz engineering sample actually scale cleanly up to 5GHz+ on production silicon.
This is why the leak is credible. An early silicon sample running well under target clocks and still matching last-gen at full clocks is exactly the curve you'd expect from a new process node in its ramp phase. The voltage-frequency curve will shift right as TSMC's N2 yields mature through 2026.
The AVX-VNNI FP16 Surprise
Buried in the Geekbench metadata is a feature flag that matters for anyone building local AI workloads: AVX-VNNI with FP16 support. This is new for Zen mobile and extends AMD's vector neural net instruction set to half-precision floats. For small-model inference — the kind laptops will increasingly do locally — this is a meaningful ISA-level capability that Zen 5 lacked. Apple has been hammering FP16 on its Neural Engine for years. AMD is finally bringing symmetric capability to the CPU side.
Timeline: 2027 for Consumers
Before anyone starts saving for a Medusa Point laptop, the reality check: Medusa Point consumer silicon is still targeting a 2027 launch window. The server-class Zen 6 EPYC 'Venice' — up to 256 cores — is coming first, later in 2026. Consumer mobile and desktop Zen 6 trail because AMD prioritizes data center margins, same as everyone else in 2026.
That said, this leak changes the calculation for anyone currently shopping Strix Point or Arrow Lake mobile. If Zen 6 delivers anything close to what this engineering sample suggests, the performance gap between a 2026 laptop and a 2027 laptop will be the biggest generational jump since the Zen 2 to Zen 3 transition. If you can wait, wait. Every nanometer counts — and N2 counts a lot.
Loading comments...